SH7763 Datasheet, PDF (1535/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
Initial
Bit Bit Name Value R/W Description
2
SF
0
R/W StartOfFrameEnable
0: Ignored
1: Interrupt due to Start of Frame is enabled.
1
WDH
0
R/W WritebackDoneHeadEnable
0: Ignored
1: Interrupt due to Writeback Done Head is enabled.
0
SO
0
R/W SchedulingOverrunEnable
0: Ignored
1: Interrupt due to Scheduling Overrun is enabled.
35.3.6 HcInterruptDisable Register (USBHID)
Writing 1 to a bit in this register clears the corresponding bit, while writing 0 to a bit leaves the bit
unchanged.
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIE OC — — — — — — — — — — — — — —
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R/W R/W R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — RHSC FNO UE RD SF WDH SO
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W
Bit
31
30
29 to 7
Bit Name Initial Value R/W
MIE
0
R/W
OC
0
R/W

All 0
R
Description
MasterInterruptDisable
This bit is a global interrupt disable. Writing 1
disables all interrupts.
OwnershipChangeDisable
0: Ignored
1: Interrupt due to Ownership Change is disabled.
Reserved
These bits are always read as 0. The write value
should always be 0
Rev. 1.00 Oct. 01, 2007 Page 1469 of 1956
REJ09B0256-0100