SH7763 Datasheet, PDF (1657/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
37.3.1 LCDC Input Clock Register (LDICKR)
This LCDC can select bus clock, the peripheral clock, or the external clock as its operation clock
source. The selected clock source can be divided using an internal divider into a clock of 1/1 to
1/32 and be used as the LCDC operating clock (DOTCLK). The clock output from the LCDC is
used to generate the synchronous clock output (LCD_CL2) for the LCD panel from the operating
clock selected in this register. For a TFT panel, LCD_CL2 = DOTCLK, and for an STN or DSTN
panel, LCD_CL2 = a clock with a frequency of (DOTCLK/data bus width of output to LCD
panel). The LDICKR must be set so that the clock input to the LCDC is 66 MHz or less regardless
of the LCD_CL2.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

 ICKSEL[1:0] 





DCDR[5:0]
Initial value: 0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
R/W: R
R R/W R/W R
R
R
R
R
R R/W R/W R/W R/W R/W R/W
Bit
15, 14
13, 12
11 to 9
8
7, 6
5 to 0
Bit Name

Initial Value R/W
All 0
R
ICKSEL[1:0] 00
R/W

All 0
R

1
R

All 0
R
DCDR[5:0] 000001
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Input Clock Select
Set the clock source for DOTCLK.
00: Setting prohibited
01: Peripheral clock is selected
10: External clock is selected
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Division Ratio
Set the input clock division ratio. For details on the
setting, refer to table 37.4.
Rev. 1.00 Oct. 01, 2007 Page 1591 of 1956
REJ09B0256-0100