SH7763 Datasheet, PDF (938/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.49 CAM Entry Table Enable Register (TSU_TEN)
TSU_TEN enables or disables the settings of TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0
to TSU_ADRL31.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEN0 TEN1 TEN2 TEN3 TEN4 TEN5 TEN6 TEN7 TEN8 TEN9 TEN10 TEN11 TEN12 TEN13 TEN14 TEN15
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TEN16 TEN17 TEN18 TEN19 TEN20 TEN21 TEN22 TEN23 TEN24 TEN25 TEN26 TEN27 TEN28 TEN29 TEN30 TEN31
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31
TEN0
0
R/W CAM Entry Table 0 (TSU_ADRH0 and TSU_ADRL0)
Setting
0: Disabled
1: Enabled
30
TEN1
0
R/W CAM Entry Table 1 (TSU_ADRH1 and TSU_ADRL1)
Setting
0: Disabled
1: Enabled
29
TEN2
0
R/W CAM Entry Table 2 (TSU_ADRH2 and TSU_ADRL2)
Setting
0: Disabled
1: Enabled
28
TEN3
0
R/W CAM Entry Table 3 (TSU_ADRH3 and TSU_ADRL3)
Setting
0: Disabled
1: Enabled
27
TEN4
0
R/W CAM Entry Table 4 (TSU_ADRH4 and TSU_ADRL4)
Setting
0: Disabled
1: Enabled
Rev. 1.00 Oct. 01, 2007 Page 872 of 1956
REJ09B0256-0100