SH7763 Datasheet, PDF (1519/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

(1) Reception Using DMA Controller
Section 34 Serial Sound Interface (SSI)
Start
Release reset,
specify configuration bits
in SSICR
Setup DMA
controller to provide data as
required for transmission
Enable SSI module,
enable DMA,
enable error interrupts
Wait for interrupt from DMAC
or SSI
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DMEN = 1,
UIEN = 1, OIEN = 1
SSI
Yes
error interrupt?
No
No
Has DMAC
Tx data been
completed?
Yes
Yes
More data to be send?
No
Disable SSI module,
disable DMA
disable error interrupt,
enable Idle interrupt
EN = 0,
DMEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module
Reset SSI module if required
End*
Note: * When SSI error interrupt occurs (underflow/overflow), back to start
and execute flow again.
Figure 34.21 Reception using DMA Controller
Rev. 1.00 Oct. 01, 2007 Page 1453 of 1956
REJ09B0256-0100