SH7763 Datasheet, PDF (385/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Section 11 Local Bus State Controller (LBSC)
The local bus state controller (LBSC) divides the external memory space and outputs control
signals corresponding to the specifications of various types of memory and bus interfaces. The
LBSC enables the connection of SRAM or ROM, etc., to this LSI. It also supports the PCMCIA
interface protocol, which is used to implement simplified system design and high-speed data
transfers in a compact system.
11.1 Features
The LBSC has the following features.
• Controls six areas, areas 0 to 2 and 4 to 6, of an external memory space divided into seven
areas.
 Maximum 64 Mbytes for each of areas 0 to 2 and 4 to 6
 Bus width of each area can be controlled through register settings (except area 0, which is
controlled by the external pin setting)
 Wait-cycle insertion by the RDY pin
 Wait-cycle insertion can be controlled by a program
 Types of memory are specifiable for connection to each area
 Output of the control signals of memory to each area
 Automatic wait cycle insertion to prevent data bus collisions on consecutive memory
accesses to different areas, or a read access followed by a write access to the same area
 Insertion of cycles to ensure the setup time and hold time to the write strobe on a write
cycle enables connection to low-speed memory
• SRAM interface
 Wait-cycle insertion can be controlled by a program
 Insertion of the wait cycle through the RDY pin
Connectable areas : 0 to 2 and 4 to 6
Settable bus widths: 32, 16, and 8 bits
• Burst ROM interface
 Wait-cycle insertion can be controlled by a program
 Burst length specified by the register
Connectable areas: 0 to 2 and 4 to 6
Settable bus widths: 32, 16, and 8 bits
Rev. 1.00 Oct. 01, 2007 Page 319 of 1956
REJ09B0256-0100