SH7763 Datasheet, PDF (142/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Table 3.11 Floating-Point Double-Precision Instructions
Instruction
Operation
FABS
DRn
DRn & H'7FFF FFFF FFFF
FFFF → DRn
FADD
DRm,DRn DRn + DRm → DRn
FCMP/EQ DRm,DRn When DRn = DRm, 1 → T
Otherwise, 0 → T
FCMP/GT DRm,DRn When DRn > DRm, 1 → T
Otherwise, 0 → T
FDIV
FCNVDS
FCNVSD
FLOAT
FMUL
FNEG
FSQRT
FSUB
FTRC
DRm,DRn DRn /DRm → DRn
DRm,FPUL double_to_ float(DRm) →
FPUL
FPUL,DRn float_to_ double (FPUL) →
DRn
FPUL,DRn (float)FPUL → DRn
DRm,DRn DRn *DRm → DRn
DRn
DRn ^ H'8000 0000 0000
0000 → DRn
DRn
√DRn → DRn
DRm,DRn DRn – DRm → DRn
DRm,FPUL (long) DRm → FPUL
Instruction Code
1111nnn001011101
1111nnn0mmm00000
1111nnn0mmm00100
1111nnn0mmm00101
1111nnn0mmm00011
1111mmm010111101
1111nnn010101101
1111nnn000101101
1111nnn0mmm00010
1111nnn001001101
1111nnn001101101
1111nnn0mmm00001
1111mmm000111101
Privileged T Bit
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New
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Compari —
son
result
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Compari —
son
result
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Table 3.12 Floating-Point Control Instructions
Instruction
Operation
Instruction Code
Privileged T Bit
LDS Rm,FPSCR Rm → FPSCR
0100mmmm01101010 —
—
LDS Rm,FPUL
Rm → FPUL
0100mmmm01011010 —
—
LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 —
—
LDS.L @Rm+,FPUL (Rm) → FPUL, Rm+4 → Rm 0100mmmm01010110 —
—
STS FPSCR,Rn
FPSCR → Rn
0000nnnn01101010 —
—
STS FPUL,Rn
FPUL → Rn
0000nnnn01011010 —
—
STS.L FPSCR,@-Rn Rn – 4 → Rn, FPSCR → (Rn) 0100nnnn01100010 —
—
STS.L FPUL,@-Rn Rn – 4 → Rn, FPUL → (Rn) 0100nnnn01010010 —
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New
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Rev. 1.00 Oct. 01, 2007 Page 76 of 1956
REJ09B0256-0100