SH7763 Datasheet, PDF (1801/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
40.2.30 Port O Data Register (PODR)
PODR is an 8-bit readable/writable register that stores port O data.
Bit: 7
6
5
4
3
2
1
0
PO7DT PO6DT PO5DT PO4DT PO3DT PO2DT PO1DT PO0DT
Initial value: 0
0 Pin state Pin state Pin state Pin state Pin state Pin state
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7
PO7DT
0
R/W Each of these bits stores output data for the
6
PO6DT
0
R/W ^{corresponding pin that is used as a general output port.}
If the port is read, the value of the corresponding bit in
5
PO5DT
Pin state R/W _{this register will be read for a pin configured as a}
4
PO4DT
Pin state R/W ^{general output port, while the state of the corresponding}
pin will be read for a pin configured as a general input
3
PO3DT
Pin state R/W _port.
2
PO2DT
Pin state R/W
1
PO1DT
Pin state R/W
0
PO0DT
Pin state R/W
Rev. 1.00 Oct. 01, 2007 Page 1735 of 1956
REJ09B0256-0100