SH7763 Datasheet, PDF (877/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Initial
Bit
Bit Name Value R/W Description
17
RXF
0
R/W Operating Mode for Receiving Port Flow Control
0: PAUSE frame detection is disabled
1: Flow control for the receiving port is enabled
16
TXF
0
R/W Operating Mode for Transmitting Port Flow Control
0: Flow control for the transmitting port is disabled
(Automatic PAUSE frame is not transmitted)
1: Flow control for the transmitting port is enabled
(Automatic PAUSE frame is transmitted as required)
15, 14 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
13
MCT
0
R/W Multicast Address Frame Receive Mode
0: Frames other than the multicast address set by the
CAM entry table 0 to 31 (H/L) registers are received.
However, if the on-chip CAM entry table reference is
disabled, all multicast address frames are received.
1: Only the multicast address set by the CAM entry
table 0 to 31 (H/L) registers is received.
12 to 10 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
MPDE
0
R/W Magic Packet Detection Enable
Enables or disables Magic Packet detection by
hardware to allow activation from the Ethernet.
0: Magic Packet detection is not enabled
1: Magic Packet detection is enabled
8, 7

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 811 of 1956
REJ09B0256-0100