SH7763 Datasheet, PDF (489/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
12.4.3 DDR-SDRAM Timing Register (STR)
STR specifies the DDR-SDRAM timing. (Details on the number range depend on the parameters
used by each memory manufacturer.
Bit:
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47
Initial value:
R/W:
Bit:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R R R R R R R R R R/W R/W R/W R/W
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8
SRFC
SWR SRRD
SRAS
7
6
5
SRC
4
3
2
1
0
SCL
SRCD SRP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
63 to 20 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
19, 18 WR
00
R/W Minimum Number of Cycles from Write command to
Read Commands
These bits specify the minimum number of cycles for
the READ command issuance after the WRITE
command is issued for the DDR-SDRAM.
00: 3 cycles
01: 4 cycles
10: 5 cycles
11: 6 cycles
Rev. 1.00 Oct. 01, 2007 Page 423 of 1956
REJ09B0256-0100