SH7763 Datasheet, PDF (822/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 Compare Match Timer (CMT)
Value in
CMCNT
CMCOR
H'00000000
Time
CMF=1
OVF=1 (When an overflow is detected)
Figure 21.3 Counter Operation (Free-Running Operation)
21.3.2 Counter Size
In this module, the size of the counter is selectable as either 16 or 32 bits. This is selected by the
CMS bit in CMCSR.
When the 16-bit size is selected, use a 32-bit value which has H'0000 as its upper half to set
CMCOR.
To detect an overflow interrupt, the value must be set to H'0000FFFF.
21.3.3 Timing for Counting by CMCNT
In this module, the clock for the counter can be selected from among the following:
• For channels 0 to 4:
 Peripheral clock (Pck0): 1/8, 1/32, or 1/128
The clock for the counter is selected by bits CKS2 to CKS0 in CMCSR. CMCNT is incremented
at the rising edge of the selected clock.
Rev. 1.00 Oct. 01, 2007 Page 756 of 1956
REJ09B0256-0100