SH7763 Datasheet, PDF (288/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 L Memory
Bit
5 to 0
Initial
Bit Name Value
R/W Description
L0SSZ
Undefined R/W L Memory Page 0 Block Transfer Source Address
Select
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
select whether the operand addresses or L0SADR
values are used as bits 15 to 10 of the transfer source
physical address for block transfer to the L memory.
L0SSZ[5:0] correspond to the transfer source physical
addresses[15:10].
0: The operand address is used as the transfer source
physical address.
1: The L0SADR value is used as the transfer source
physical address.
Settable values:
111111: Transfer source physical address is specified
in 1-Kbyte units.
111110: Transfer source physical address is specified
in 2-Kbyte units.
111100: Transfer source physical address is specified
in 4-Kbyte units.
111000: Transfer source physical address is specified
in 8-Kbyte units.
110000: Transfer source physical address is specified
in 16-Kbyte units.
100000: Transfer source physical address is specified
in 32-Kbyte units.
000000: Transfer source physical address is specified
in 64-Kbyte units.
Settings other than the ones given above are
prohibited.
Rev. 1.00 Oct. 01, 2007 Page 222 of 1956
REJ09B0256-0100