SH7763 Datasheet, PDF (1077/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
25.3.5 Time Stamp Counter Registers 0, 1 (STITSC0, STITSC1)
STITSC is used to count the time stamp.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS[31:16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TS[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
31 to 0 TS[31:0] All 0
R/W Description
R/W Time Stamp Counter
• When time stamp is used
At reception: Starts counting from reception of the
first packet. Counting can be started from any
desired value by setting the value before reception.
However, this register cannot be written to during
reception of a packet.
At transmission: Starts counting from transmission
of the first packet. Counting can be started from any
desired value by setting the value before
transmission. However, this register cannot be
written to during transmission of a packet.
• When fixed value is used
At reception: This register value is added to the
front of a packet as a fixed value.
Rev. 1.00 Oct. 01, 2007 Page 1011 of 1956
REJ09B0256-0100