SH7763 Datasheet, PDF (1499/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
26
OIRQ
0
R/W*¹ Overflow Error Interrupt Status Flag
This status flag indicates that the data has been
supplied at a higher rate than the required rate.
This bit is set to 1 regardless of the setting of OIEN bit.
In order to clear it to 0, write 0 in it.
If OIRQ = 1 and OIEN = 1, then an interrupt will be
generated.
When TRMD = 0 (Receive Mode):
If OIRQ = 1, it indicates that the previous unread data
had not been read out before new unread data was
written in SSIRDR. This may cause the loss of data,
which can lead to destruction of multi-channel data.
Note: When overflow error occurs, the data in the data
buffer will be overwritten by the next data sent
from the SSI interface.
When TRMD = 1 (Transmit Mode):
If OIRQ = 1, it indicates that SSITDR had data written in
before the data in SSITDR was transferred to the shift
register. This may cause the loss of data, which can
lead to destruction of multi-channel data.
25
IIRQ
0*²
R
Idle Mode Interrupt Status Flag
This status flag indicates whether the SSI module is in
the idle status. This bit is set to 1 regardless of the
setting of IIEN bit, so that polling will be possible.
The interrupt can be masked by clearing IIEN bit to 0,
but writing 0 in this bit will not clear the interrupt.
If IIRQ = 1 and IIEN = 1, then an interrupt will be
generated.
0: The SSI module is not in the idle status.
1: The SSI module is in the idle status.
Rev. 1.00 Oct. 01, 2007 Page 1433 of 1956
REJ09B0256-0100