SH7763 Datasheet, PDF (1791/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
40.2.20 Port E Data Register (PEDR)
PEDR is an 8-bit readable/writable register that stores port E data.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
— PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7

All0
R
Reserved
6
These bits are always read as 0, and the write value
should always be 0.
5
PE5DT
0
R/W Each of these bits stores output data for the
4
PE4DT
0
R/W ^{corresponding pin that is used as a general output port.}
If the port is read, the value of the corresponding bit in
3
PE3DT
0
R/W _{this register will be read for a pin configured as a}
2
PE2DT
0
R/W ^{general output port, while the state of the}
corresponding pin will be read for a pin configured as a
1
PE1DT
0
R/W _{general input port.}
0
PE0DT
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 1725 of 1956
REJ09B0256-0100