SH7763 Datasheet, PDF (1064/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
Figure 25.1 shows a block diagram of the STIF.
Perioheral clock 0
(Pck 0)
Peripheral bus
interface
Channel 0
Stream
interface
control unit
FIFO register
Stream interface (STIF)
Channel 1
Peripheral bus
interface
Stream
interface
control unit
FIFO register
ST0_CLK/ST0_STRB
ST0_REQ
ST0_START
ST0_VALID
ST0_D7 to ST0_D0
ST0M_CLKIO/ST0M_STRBI
ST0M_REQO
ST0M_STARTI
ST0M_VALIDI
ST0M_D7I to ST0M_D0I
ST1_CLK/ST1_STRB
ST1_REQ
ST1_START
ST1_VALID
ST1_D7 to ST1_D0
Figure 25.1 Block Diagram of STIF
Rev. 1.00 Oct. 01, 2007 Page 998 of 1956
REJ09B0256-0100