SH7763 Datasheet, PDF (79/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

1.2 Block Diagram
Section 1 Overview
CPU
FPU
I-cache
MMU
O-cache
PCIC
EXCPU
LBSC
PCC
(External bus)
(External bus)
(External bus)
UBC
DDRIF
(External bus)
AUD
LRAM
SECURITY*
GETHER
USBH
USBF
SBR
LCDC
HPB
DMAC
6 channels
CPG
INTC
CMT
MMCIF
RTC
SIM
SIOF
3 channels
SCIF
3 channels
IIC
2 channels
SSI
4 channels
[Legend]
AUD:
Advanced user debugger
CMT:
Compare match timer
CPG:
Clock pulse generator
CPU:
Central processing unit
DDRIF: DDR-SDRAM interface
DMAC: Direct memory access controller
FPU:
Floating-point unit
GPIO:
General purpose I/O
SBR:
SuperHyway bridge
HPB:
Peripheral bus bridge
I-Cache: Instruction cache
INTC:
Interrupt controller
LBSC:
Local bus state controller
PCC:
PC card controller
LRAM:
L memory
MMCIF: Multimedia card interface
MMU:
Memory management unit
O-Cache: Operand (data) cache
PCIC:
PCI controller
EXCPU: External CPU interface
RTC:
Realtime clock
UBC:
User break controller
H-UDI:
User debugging interface
GETHER: Gigabit Ethernet controller
SECURITY*:Security accelerator
USBH:
USB host controller
TMU
AD/DA
TPU
WDT
H-UDI
HAC
STIF
2 channels
GPIO
USBF:
SCIF:
SIOF:
SSI:
STIF:
HAC:
AD/DA:
TMU:
IIC:
WDT:
SIM:
TPU:
LCDC:
USB function controller
Serial communication interface with FIFO
Serial I/O with FIFO
Serial sound interface
Stream interface
Audio codec interface
A/D converter, D/A converter
Timer unit
IIC bus interface
Watchdog timer
SIM card module
16-bit pulse unit
LCD controller
Note: * SECURITY is incorporated only in the R5S77630, not in the R5S77631.
Figure 1.1 SH7763 Block Diagram
Rev. 1.00 Oct. 01, 2007 Page 13 of 1956
REJ09B0256-0100