SH7763 Datasheet, PDF (1532/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
Bit
Bit Name Initial Value R/W Description
0
HCR
0
R/W HostControllerReset
This bit is set to initiate a software reset. This bit is
cleared by the Host Controller upon completion of
the reset operation.
35.3.4 HcInterruptStatus Register (USBHIS)
All bits are set by hardware and cleared by software.
These bits in this register can be cleared by writing 1 to bit positions to be cleared.
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— ———————————————
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — RHSC FNO UE RD SF WDH SO
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 7
6
5
4
3
Bit Name

RHSC
FNO
UE
RD
Initial Value R/W
All 0
R
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0
RootHubStatusChange
This bit is set when the content of HcRhStatus
register or the content of any HcRhPortStatus
register has changed.
FrameNumberOverflow
This bit is set when bit 15 of FrameNumber
changes value from 0 to 1 or from 1 to 0.
UnrecoverableError
This bit is set when HC detects a system error that
is not USB related.
ResumeDetected
This bit is set when the Host Controller detects
resume signaling on a downstream port.
Rev. 1.00 Oct. 01, 2007 Page 1466 of 1956
REJ09B0256-0100