SH7763 Datasheet, PDF (1213/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.12 Line Status Register (SCLSR)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
               ORER
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W*¹
Initial
Bit
Bit Name Value R/W Description
15 to 1 —
All 0
R
Reserved
0
ORER
0
These bits are always read as 0. The write value should
always be 0.
R/W*¹ Overrun Error
Indicates that an overrun error occurred during
reception, causing abnormal termination.
0: Reception in progress, or reception has ended
normally*²
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ORER after reading ORER = 1
1: An overrun error occurred during reception*³
[Setting condition]
• When the next serial reception is completed while
SCFRDR receives 16-byte data (SCFRDR is full)
Notes: 1. Only 0 can be written, to clear the flag.
2. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR
is cleared to 0.
3. The receive data prior to the overrun error is retained in SCFRDR, and the data
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1.
To resume data reception after clearing the ORER flag, be sure to first read (or clear)
data in the receive FIFO and handle the error, then clear the ORER flag.
Rev. 1.00 Oct. 01, 2007 Page 1147 of 1956
REJ09B0256-0100