SH7763 Datasheet, PDF (653/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
14.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2)
DMARS is 16-bit readable/writable registers that specify the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer request of CMT, SCIF0 to SCIF2. HAC, USBF, SSI0 to SSI3, MMCIF, SIM, SIOF0 to
SIOF2, STIF0, AND STIF1.
When MID/RID other than the values listed in table 14.4 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits RS[3:0]
has been set to B'1000 for CHCR0 to CHCR5 registers. Otherwise, even if DMARS has been set,
transfer request source is not accepted.
• DMARS0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
C1MID[5:0]
C1RID[1:0]
C0MID[5:0]
C0RID[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
15 to 10 C1MID[5:0] 000000 R/W
9, 8
C1RID[1:0] 00
R/W
7 to 2 C0MID[5:0] 000000 R/W
1, 0
C0RID[1:0] 00
R/W
Descriptions
Transfer request module ID for DMA channel 1 (MID)
See table 14.4.
Transfer request register ID for DMA channel 1 (RID)
See table 14.4.
Transfer request module ID for DMA channel 0 (MID)
See table 14.4
Transfer request register ID for DMA channel 0 (RID)
See table 14.4.
Rev. 1.00 Oct. 01, 2007 Page 587 of 1956
REJ09B0256-0100