SH7763 Datasheet, PDF (407/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Initial
Bit
Bit Name Value R/W Description
31

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
30 to 28 IWW
111
R/W Idle Cycles between Write-Read/Write-Write
Specify the number of idle cycles to be inserted after an
access to a memory connected to the space is
completed. The target cycles are write-read cycles and
write-write cycles. For details, see section 11.5.8, Wait
Cycles between Accesses.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
27

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
26 to 24 IWRWD 111
R/W Idle Cycles between Read-Write to Different Spaces
Specify the number of idle cycles to be inserted after an
access to a memory connected to the space is
completed. The target cycles are read-write cycles to
different spaces. For details, see section 11.5.8, Wait
Cycles between Accesses.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 341 of 1956
REJ09B0256-0100