SH7763 Datasheet, PDF (1462/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
33.3.2 Command/Status Address Register (HACCSAR)
HACCSAR is a 32-bit read/write register that specifies the address of the codec register to be read
/written. When requesting a write to/read from a codec register, write the command register
address to HACCSAR. Then the HAC transmits this register address to the codec via slot 1.
After the codec has responded to a read request (HACRSR.STARY = 1), the status address
received via slot 1 can be read out from HACCSAR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − − − − − − − − − − − ^{RW CA/SA[6:4]}
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CA/SA[3:0]
SLREQ[3:12]
−−
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W
31 to 20 
All 0 R
19
RW
0
R/W
Description
Reserved
Always 0 for read and write.
Codec Read/Write Command
0: Notifies the off-chip codec device of a write access to
the register specified in the address field (CA6/SA6
to CA0/SA0).
Write the data to HACCSDR in advance.
When HACACR.TX12_ATOMIC is 1, the HAC
transmits HACCSAR and HACCSDR as a pair in the
same Tx frame.
When HACACR.TX12_ATOMIC is 0, transmission of
HACCSAR and HACCSDR in the same Tx frame is
not guaranteed.
1: Notifies the off-chip codec device of a read access to
the register specified in the address field (CA6/SA6
to CA0/SA0).
Rev. 1.00 Oct. 01, 2007 Page 1396 of 1956
REJ09B0256-0100