SH7763 Datasheet, PDF (121/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 2 Programming Model
2.7 Usage Note
2.7.1 Notes on Self-Modified Codes*
This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the
processing speed. Therefore if the instruction in the memory is modified and it is executed
immediately, then the pre-modified code that is prefetched are likely to be executed. In order to
execute the modified code definitely, one of the following sequences should be executed between
the execution of modifying codes and modified codes.
(1) In case the modified codes are in non-cacheable area
SYNCO
ICBI @Rn
The target for the ICBI instruction can be any address within the range where no address error
exception occurs.
(2) In case the modified codes are in cacheable area (write-through)
SYNCO
ICBI @Rn
The all instruction cache area corresponding to the modified codes should be invalidated by the
ICBI instruction. The ICBI instruction should be issued to each cache line. One cache line is 32
bytes.
(3) In case the modified codes are in cacheable area (copy-back)
OCBP @Rm or OCBWB @Rm
SYNCO
ICBI @Rn
The all operand cache area corresponding to the modified codes should be written back to the
main memory by the OCBP or OCBWB instruction. Then the all instruction cache area
corresponding to the modified codes should be invalidated by the ICBI instruction. The OCBP,
OCBWB and ICBI instruction should be issued to each cache line. One cache line is 32 bytes.
Note: * Processes executed while changing the instructions on the memory dynamically.
Rev. 1.00 Oct. 01, 2007 Page 55 of 1956
REJ09B0256-0100