SH7763 Datasheet, PDF (874/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.2 E-MAC Mode Register (ECMR)
ECMR is a 32-bit readable/writable register that specifies the operating mode of the GETHER.
The settings in this register are normally made in the initialization process following a reset.
The operating mode setting must not be changed while the transmitting and receiving functions
are enabled. To switch the operating mode, return the E-MAC and E-DMAC to their initial states
by means of the SWRT and SWRR bits in EDMR before making settings again.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16




 TRCCM 
 RCSC  DPAD RZPF ZPF PFR RXF TXF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R R R/W R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8

 MCT 

 MPDE 
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R/W R R R R/W R
7
6
5
4
3
2
1
0
 RE TE  ILB  DM PRM
0
0
0
0
0
0
0
0
R R/W R/W ^R R/W R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 27 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
26
TRCCM 0
R/W Counter Clear Mode
Sets the method for clearing the counter register. Refer
to the description of each register.
0: Cleared to 0 by writing H'11111111 to the relevant
register
1: Cleared to 0 when the relevant register is read
25, 24 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 808 of 1956
REJ09B0256-0100