SH7763 Datasheet, PDF (1605/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.30 FIFO Clear Register 1 (FCLR1)
FCLR is a one shot register to clear the FIFO buffers for endpoints 4 and 5. Writing 1 to a bit
clears the data in the corresponding FIFO buffer.
The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer
during transmission and reception.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
EP5
CCLR
—
—
EP5 EP4
CLR CLR
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R W W W W W W W W
Bit Bit Name
31 to 8 
7 to 5 
4
EP5 CCLR
3, 2 
1
EP5 CLR
0
EP4 CLR
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
Undefined W Reserved
The write value should always be 0.
Undefined W EP5 CPU Clear
Undefined W Reserved
The write value should always be 0.
Undefined W EP5 Clear
Undefined W EP4 Clear
Rev. 1.00 Oct. 01, 2007 Page 1539 of 1956
REJ09B0256-0100