SH7763 Datasheet, PDF (1653/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
37.2 Input/Output Pins
Table 37.1 summarizes the LCDC's pin configuration.
The LCDC output pins are divided in two groups: normal output group and mirror output group.
The input/output operations of pins in two groups are always the same. The pin select register of
the PFC is used to select the LCDC pins. As pins in two groups have different input/output timing,
mixed use of pins in two groups is not allowed.
Table 37.1 Pin Configuration
Pin
Normal Output Mirror Output
I/O
Function
LCD_D15 to 0
LCDM_D15 to 0
Output Data for LCD panel
LCD_DON
LCDM_DON
Output Display-on signal (DON)
LCD_CL1
LCDM_CL1
Output Shift-clock 1 (STN/DSTN)/horizontal sync
signal (HSYNC) (TFT)
LCD_CL2
LCDM_CL2
Output Shift-clock 2 (STN/DSTN)/dot clock (DOTCLK)
(TFT)
LCD_M_DISP
LCDM_M_DISP
Output LCD current-alternating signal/DISP signal
LCD_FLM
LCDM_FLM
Output First line marker/vertical sync signal (VSYNC)
(TFT)
LCD_VCPWC
LCDM_VCPWC
Output LCD-module power control (VCC)
LCD_VEPWC
LCDM_VEPWC
Output LCD-module power control (VEE)
LCD_CLK*
Input LCD clock-source input
Note: Check the LCD module specifications carefully in section 37.5, Clock and LCD Data
Signal Examples, before deciding on the wiring specifications for the LCD module.
* Only this pin is available as the LCD_CLK pin in the LCDC module.
Rev. 1.00 Oct. 01, 2007 Page 1587 of 1956
REJ09B0256-0100