SH7763 Datasheet, PDF (59/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 11.15 Relationship between Address and CE When Using PCMCIA Interface ......... 380
Section 12 DDR-SDRAM Interface (DDRIF)
Table 12.1 Pin Configuration.................................................................................................... 81
Table 12.2 Access and Data Alignment in Little Endian Mode
(External Bus Width is 32 Bits) .............................................................................. 82
Table 12.3 Access and Data Alignment in Big Endian Mode
(External Bus Width is 32 Bits) .............................................................................. 83
Table 12.4 Register Configuration............................................................................................ 85
Table 12.5 Register State in Each Operating Mode .................................................................. 86
Table 12.6 DDR-SDRAM Commands Issued by DDRIF ...................................................... 102
Table 12.7 DDR-SDRAM Address Multiplexing (32-Bit Data Bus) ..................................... 106
Section 13 PCI Controller (PCIC)
Table 13.1 Input/Output Pins.................................................................................................... 82
Table 13.2 List of PCIC Registers ............................................................................................ 85
Table 13.3 Register States in Each Operating Mode ................................................................ 88
Table 13.4 Supported Bus Commands.................................................................................... 157
Table 13.5 PCIC Address Map ............................................................................................... 159
Table 13.6 Interrupt Priority ................................................................................................... 178
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1 Pin Configuration.................................................................................................... 81
Table 14.2 Register Configuration of DMAC........................................................................... 83
Table 14.3 State of Registers in Each Operating Mode ............................................................ 85
Table 14.4 Transfer Request Sources ..................................................................................... 103
Table 14.5 Setting External Request Mode with RS bit ......................................................... 105
Table 14.6 Selecting External Request Detection with DL, DS Bits ...................................... 106
Table 14.7 Selecting External Request Detection with DO Bit .............................................. 106
Table 14.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0] ........... 107
Table 14.9 DMA Transfer Matrix in Auto-Request Mode (all channels)............................... 117
Table 14.10 DMA Transfer Matrix in External Request Mode (only channels 0 to 3)......... 118
Table 14.11 DMA Transfer Matrix in On-Chip Peripheral module Request Mode.............. 119
Table 14.12 Register Setting for SRAM, Burst ROM, Byte Control SRAM Interface. ....... 131
Table 14.13 Register Setting for PCMCIA Interface............................................................ 132
Table 14.14 Register Setting for MPX Interface (Read Access) .......................................... 132
Table 14 15 Register Settings for MPX Interface (Write Access) ........................................ 132
Section 15 External CPU Interface (EXCPU)
Table 15.1 Pin Configuration.................................................................................................. 612
Table 15.2 Register Configuration.......................................................................................... 613
Table 15.3 Register States in Each Operating Mode .............................................................. 613
Rev. 1.00 Oct. 01, 2007 Page lix of lxvi