SH7763 Datasheet, PDF (668/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
• Burst Mode (LCKN = 0, TB = 1)
In burst mode, once the DMAC obtains the SuperHyway bus mastership, the transfer is
performed continuously without releasing the bus mastership until the transfer end condition is
satisfied. In external request mode with level detection of the DREQ pin, however, when the
DREQ pin is not active, the bus mastership passes to the other bus master after the DMAC
transfer request that has already been accepted ends, even if the transfer end conditions have
not been satisfied.
Burst mode cannot be used when the on-chip peripheral module is the transfer request source.
Figure 14.9 shows DMA transfer timing in burst mode.
DREQ
SuperHyway
bus cycle
CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Read Write Read Write Read Write
Figure 14.9 DMA Transfer Timing Example in Burst Mode
(DREQ Low Level Detection)
(3) DMA Transfer Matrix
Table 14.10 shows the DMA transfer matrix in auto-request mode and table 14.11 shows the
DMA transfer matrix in external request mode, and table 14.12 shows the on-chip peripheral
module request.
Rev. 1.00 Oct. 01, 2007 Page 602 of 1956
REJ09B0256-0100