SH7763 Datasheet, PDF (375/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

9.7 Usage Notes
Section 9 Interrupt Controller (INTC)
9.7.1
Example of Interrupt Handling Routine for Level-Encoded IRL and Level-Sensed
IRQ
If an interrupt request is accepted when level-sensed IRQ or level-encoded IRL interrupt request is
selected, the held request must be cleared in the interrupt handling routine. Figure 9.5 shows an
example of clearing the interrupt request held in the detection circuit.
Start of level-encoded IRL or level-sensed IRQ interrupt
handing
Interrupt handing
Clear the level-encoded IRL or level-sensed IRQ interrupt
request source.
Notify acceptance of the interrupt to external devices by
using GPIO output or local bus space.
1. Write to the GPIO register or
local bus space.
2. Read the address to which
writing has been made.
Wait for the level-encoded IRL or level-sensed IRQ
interrupt request to be cleared.
An appropriate time is necessary for the interrupt request
input to the IRQ/IRL pin to be cancelled and for the INTC
to detect the cancellation (more than 8 bus clock cycles).
Clear the interrupt request held in the detection circuit.
Set the corresponding mask bit to 1 to clear the interrupt
request held in the detection circuit.
1. Set the corresponding bit in
INTMSK0/INTMSK1.
2. Set the corresponding bit in
INTMSKCLR0/INTMSKCLR1.
3. Read INTMSK0/INTMSK1.
End of level-encoded IRL or level-sensed IRQ interrupt
handing
Figure 9.5 Example of Interrupt Handling Routine
After the CPU accepts an interrupt request, acceptance of the request should be notified to the
external devices and the request should be cancelled. For example, acceptance can be notified by
outputting the accepted level and pin-related information via the GPIO (general I/O port) and
writing the acceptance information to a specific address in the local bus space. Here, writing to the
GPIO register or local bus space and reading from the location should be consecutively executed.
When clearing the interrupt requests held in the detection circuit, adequate time is necessary for
the CPU to detect the cancellation of the interrupt request. To secure the time, writing to
Rev. 1.00 Oct. 01, 2007 Page 309 of 1956
REJ09B0256-0100