SH7763 Datasheet, PDF (1690/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
Figure 37.2 shows the valid display and the retrace period.
Hsync Signal
H Total Time
H AddressableVideo
Vsync Time
Back Porch
Top Border
V Addressable
Video
Bottom Border
Front Porch
Active Video =Top/Left Border + Addressable Video + Bottom/Right Border
Total H Blank = Hsync Time + Back Porch + Front Porch
Total V Blank = Vsync Time + Back Porch + Front Porch
HTCN = H Total Time
HDCN = H Addressable Video
HSYNP = H Addressable Video + Right Border + Front Porch
HSYNW = Hsync Time
VTLN = V Total Time
CDLN = V Addressable Video
VSYNP = V Addressable Video + Bottom Border + Front porch
VSYNW = Vsync Time
Figure 37.2 Valid Display and the Retrace Period
Rev. 1.00 Oct. 01, 2007 Page 1624 of 1956
REJ09B0256-0100