SH7763 Datasheet, PDF (42/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.1 DDRIF Block Diagram ........................................................................................... 410
Figure 12.2 Data Alignment in DDR-SDRAM and DDRIF....................................................... 414
Figure 12.3 Relationship between Write Values in SDMR and Output Signals to
Memory Pins ........................................................................................................... 428
Figure 12.4 DDR-SDRAM Access............................................................................................. 430
Figure 12.5 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes;
Without Auto-Precharge) ........................................................................................ 438
Figure 12.6 Basic DDRIF Timing (1 Burst Write: 1, 2, 4, or 8 Bytes;
Without Auto-Precharge) ........................................................................................ 439
Figure 12.7 Basic DDRIF Timing
(1 Burst Read: 1, 2, 4, or 8 Bytes; With Auto-Precharge)....................................... 440
Figure 12.8 Basic DDRIF Timing
(1 Burst Write: 1, 2, 4, or 8 Bytes; With Auto-Precharge)...................................... 441
Figure 12.9 Basic DDRIF Timing (4 Burst Read: 32 Bytes; Without Auto-Precharge)............. 442
Figure 12.10 Basic DDRIF Timing (4 Burst Write: 32 Bytes; Without Auto-Precharge).......... 443
Figure 12.11 Basic DDRIF Timing
(Precharge all Banks (PREALL) to Bank Activate (ACT)).................................. 444
Figure 12.12 Basic DDRIF Timing (Mode Register Set (MRS)) ............................................... 445
Figure 12.13 Basic DDRIF Timing
(Auto-Refresh (REFA) Enter/Exit to Bank Activate (ACT)) ............................... 446
Figure 12.14 Basic DDRIF Timing (Self-Refresh Entry from IDLE (REFS)/
Self-Refresh Exit (REFSX) to Any Command Input)........................................... 447
Section 13 PCI Controller (PCIC)
Figure 13.1 PCIC Block Diagram .............................................................................................. 451
Figure 13.2 SuperHyway Bus to PCI Local Bus Access ............................................................ 530
Figure 13.3 SuperHyway Bus to PCI Local Bus Address Translation
(PCI Memory Space 0)............................................................................................ 531
Figure 13.4 SuperHyway Bus to PCI Local Bus Address Translation
(PCI Memory Space 1)............................................................................................ 532
Figure 13.5 SuperHyway Bus to PCI Local Bus Address Translation
(PCI Memory Space 2)............................................................................................ 532
Figure 13.6 SuperHyway Bus to PCI Local Bus Address Translation (PCI I/O) ....................... 533
Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Local bus
(Non-Byte Swapping: TBS = 0).............................................................................. 535
Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local bus
(Byte Swapping: TBS = 1) ...................................................................................... 536
Figure 13.9 PCI local bus to SuperHyway bus Memory Map .................................................... 537
Rev. 1.00 Oct. 01, 2007 Page xlii of lxvi