SH7763 Datasheet, PDF (1234/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(4) Serial Data Transmission (Clocked Synchronous Mode)
Figure 28.14 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Initialization
Start of transmission
Read TDFE flag in SCFSR
[1]
[1] SCIF initialization:
See sample SCIF initialization flowchart in figure 28.13.
[2] SCIF status check and transmit data write:
Read SCFSR and check that the TDFE flag is set to 1,
[2]
then write transmit data to SCFTDR, and clear
the TDFE flag to 0.
No
TDFE = 1?
Yes
Write transmit data to SCFTDR
and clear TDFE flag and
TEND flag in SCFSR to 0
[3] Serial transmission continuation procedeure:
To continue serial transmission, read 1 from the TDFE
flag to confirm that writing is possible, them write data
to SCFTDR, and then clear the TDFE flag to 0.
All data transmitted?
Yes
No
[3]
Read TEND flag in SCFSR
No
TEND = 1?
Yes
Clear TE bit in SCSCR to 0
End of transmission
Note: In clock synchronous mode, when transmit data is written to the SCFTDR by the DMAC,
the TEND flag may no be cleared. Therefore, if the DMAC is used for transmission in
clock synchronous mode, read the TEND flag in the following method.
1. Confirm data transfer completion on the DMAC side.
2. Read the TEND flag.
3. Clear the TEND flag to 0 when TEND = 1.
4. Read the TEND flag again.
5. Use the TEND flag read for the second time.
Figure 28.14 Sample Serial Transmission Flowchart
Rev. 1.00 Oct. 01, 2007 Page 1168 of 1956
REJ09B0256-0100