SH7763 Datasheet, PDF (1552/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
35.3.22 HcRhPortStatus[2] Register (USBHRPS2)
This register is reset by the UsbReset state.
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — — PRSC OCIC PSSC PESC CSC
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — LSDA PPS — — — PRS POCI PSS PES CCS
Initial value : 0
0
0
0
0
0—0
0
0
0
0
0
0
0
0
R/W : R R R R R R R/W R/W R R R R/W R/W R/W R/W R/W
Bit
Bit Name Initial value
31 to 21 
All 0
20
PRSC
0
19
OCIC
0
18
PSSC
0
17
PESC
0
R/W Description
R Reserved
These bits are always read as 0. The write value
should always be 0.
R/W PortResetStatusChange
This bit indicates that the port reset signal has
completed.
0: Port reset is not complete.
1: Port reset is complete.
R/W PortOverCurrentIndicatorChange
This bit is set when OverCurrentIndicator changes.
Writing 1 clears this bit. Writing 0 has no effect.
R/W PortSuspendStatusChange
This bit indicates the completion of the selective
resume sequence for the port.
0: Port is not resumed.
1: Port resume is complete.
R/W PortEnableStatusChange
This bit indicates that the port has been disabled due
to a hardware event (PortEnableStatus bit is cleared).
0: Port has not been disabled.
1: PortEnableStatus bit has been cleared.
Rev. 1.00 Oct. 01, 2007 Page 1486 of 1956
REJ09B0256-0100