SH7763 Datasheet, PDF (64/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 37.3
Table 37.4
Table 37.5
Table 37.6
Table 37.7
Table 37.8
Register State in Each Operating Mode.................................................................. 83
I/O Clock Frequency and Clock Division Ratio ..................................................... 86
Limits on the Resolution of Rotated Displays, Burst Length, and Connected
Memory (32-bit SDRAM) .................................................................................... 119
Available Power-Supply Control-Sequence Periods at Typical Frame Rates....... 130
LCDC Operating Modes....................................................................................... 131
LCD Module Power-Supply States....................................................................... 131
Section 38 A/D Converter
Table 38.1 Pin Configuration................................................................................................ 1643
Table 38.2 Register Configuration........................................................................................ 1644
Table 38.3 Register State in Each Operating Mode.............................................................. 1644
Table 38.4 Analog Input Channels and A/D Data Registers................................................. 1645
Table 38.5 A/D Conversion Time......................................................................................... 1654
Table 38.6 Relationship between Clock Division Ratio and Usable Pck0 Clock Frequency1658
Section 39 D/A Converter (DAC)
Table 39.1 Pin Configuration................................................................................................ 1660
Table 39.2 Register Configuration........................................................................................ 1660
Table 39.3 Register State in Each Operating Mode.............................................................. 1660
Section 40 General Purpose I/O (GPIO)
Table 40.1 Multiplexed Pins Controlled by Port Control Registers ......................................... 80
Table 40.2 Register Configuration (1) ...................................................................................... 90
Table 40.3 Register States in Each Operating Mode ................................................................ 92
Section 41 User Break Controller (UBC)
Table 41.1 Register Configuration........................................................................................ 1747
Table 41.2 Register Status in Each Processing State ............................................................ 1748
Table 41.3 Settings for Match Data Setting Register............................................................ 1762
Table 41.4 Relation between Operand Sizes and Address Bits to be Compared .................. 1771
Section 42 User Debugging Interface (H-UDI)
Table 42.1 Pin Configuration................................................................................................ 1785
Table 42.2 Commands Supported by Boundary-Scan TAP Controller ................................ 1787
Table 42.3 Register Configuration (1) .................................................................................. 1788
Table 42.4 Register Configuration (2) .................................................................................. 1788
Table 42.5 Register Status in Each Processing State ............................................................ 1788
Table 42.6 SDBSR Configuration ........................................................................................ 1792
Section 43 Electrical Characteristics
Table 43.1 Absolute Maximum Ratings ................................................................................... 79
Table 43.2 Power-On and Power-Off Timing .......................................................................... 81
Rev. 1.00 Oct. 01, 2007 Page lxiv of lxvi