SH7763 Datasheet, PDF (815/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 Compare Match Timer (CMT)
21.2 Register Descriptions
Table 21.2 shows the CMT register configuration. Table 21.3 shows the register state in each
operating mode.
Table 21.1 Register Configuration
Register Name
Area P4
Area 7
Access
Abbreviation R/W Address* Address* Size
Compare match timer start register CMSTR
R/W H'FFE2 0000 H'1FE2 0000 16
Compare match timer control/status CMCSR_0 R/W H'FFE2 0010 H'1FE2 0010 16
register_0
Compare match timer counter_0 CMCNT_0 R/W H'FF20 0014 H'1F20 0014 32
Compare match timer constant
register_0
CMCOR_0 R/W H'FF20 0018 H'1F20 0018 32
Compare match timer control/status CMCSR_1 R/W H'FFE2 0020 H'1FE2 0020 16
register_1
Compare match timer counter_1 CMCNT_1 R/W H'FF20 0024 H'1F20 0024 32
Compare match timer constant
register_1
CMCOR_1 R/W H'FF20 0028 H'1F20 0028 32
Compare match timer control/status CMCSR_2 R/W H'FFE2 0030 H'1FE2 0030 16
register_2
Compare match timer counter_2 CMCNT_2 R/W H'FF20 0034 H'1F20 0034 32
Compare match timer constant
register_2
CMCOR_2 R/W H'FF20 0038 H'1F20 0038 32
Compare match timer control/status CMCSR_3 R/W H'FFE2 0040 H'1FE2 0040 16
register_3
Compare match timer counter_3 CMCNT_3 R/W H'FF20 0044 H'1F20 0044 32
Compare match timer constant
register_3
CMCOR_3 R/W H'FF20 0048 H'1F20 0048 32
Compare match timer control/status CMCSR_4 R/W H'FFE2 0050 H'1FE2 0050 16
register_4
Compare match timer counter_4 CMCNT_4 R/W H'FF20 0054 H'1F20 0054 32
Compare match timer constant
register_4
CMCOR_4 R/W H'FF20 0058 H'1F20 0058 32
Note: * P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.
Rev. 1.00 Oct. 01, 2007 Page 749 of 1956
REJ09B0256-0100