SH7763 Datasheet, PDF (1904/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 43 Electrical Characteristics
43.4.2 Control Signal Timing
Table 43.10 Control Signal Timing
Conditions:
V_CCQ = VDD_RTC = AV_CC = 3.0 to 3.6 V, V_CCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to
1.35 V, Ta = −20 to 75°C
Item
BREQ setup time
BREQ hold time
BACK delay time
Bus three-state delay time
Bus buffer on time
STATUS0, STATUA1 delay time
Note: t : One CLK cycle time
cyc
Symbol
t
BREQS
t_BREQH
t_BACKD
t
BOFF1
t
BON1
t
STD
Min.
6
3
1



Max. Unit
 ns
 ns
13 ns
13 ns
13 ns
20 ns
Figure
43.9
43.9
43.9
43.9
43.9
43.10
CLKOUT
BREQ
BACK
A[25:0], CSn, BS,
RDWR, CE2A,
CE2B, WEn, RD
t_BREQH
t_BREQS
t_BREQH
t_BACKD
t_BREQS
t_BACKD
t_BOFF1
t_BON1
Figure 43.9 Control Signal Timing
Rev. 1.00 Oct. 01, 2007 Page 1838 of 1956
REJ09B0256-0100