SH7763 Datasheet, PDF (338/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
9.3.16 Interrupt Source Register (Mask State is affected) (INT2A1)
INT2A1 (mask state is affected) is a 32-bit read-only register that indicates interrupt source
modules. Note that if interrupt masking is set in the interrupt mask register, INT2A1 does not
indicate a source module in a corresponding bit. To check whether interrupts are generated,
regardless of the state of the interrupt mask register, use INT2A0
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − − − − − − − GPIO
SSI0 MMCIF
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− − − − PCIC1 PCIC0 HAC CMT
DMAC H-UDI
WDT SCIF1 SCIF0 RTC TMU1 TMU0
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Initial
Bit
Bit Name Value
31 to 26 —
All 0
25
GPIO
0
24
—
0
23
SSI0
0
22
MMCIF 0
21
—
0
20
SIOF0 0
19
PCIC5 0
18
PCIC4 0
R/W
R
R
R
R
R
R
R
R
R
Function
Description
These bits are always read as Indicates interrupt
0. The write value should
sources for each
always be 0.
peripheral module
Indicates GPIO interrupt source ^{(INT2A1 is affected}
by the state of the
This bit is always read as 0. _{interrupt mask}
The write value should always _register).
be 0.
0: No interrupts
Indicates SSI0 interrupt source _{1: Interrupts are}
Indicates MMCIF interrupt
generated
source
Note: Reading the
This bit is always read as 0.
The write value should always
be 0.
Indicates SIOF0 interrupt
source
INTEVT code
notified to the
CPU directly
can identify
interrupt
sources. In this
Indicates PCIC5 interrupt
case, reading
source
INT2A1 is not
Indicates PCIC4 interrupt
necessary.
source
Rev. 1.00 Oct. 01, 2007 Page 272 of 1956
REJ09B0256-0100