SH7763 Datasheet, PDF (316/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
31 to 28 IP0
H'0
R/W Set priority of an independent interrupt request of IRQ0.
27 to 24 IP1
H'0
R/W Set priority of an independent interrupt request of IRQ1.
23 to 20 IP2
H'0
R/W Set priority of an independent interrupt request of IRQ2.
19 to 16 IP3
H'0
R/W Set priority of an independent interrupt request of IRQ3.
15 to 12 IP4
H'0
R/W Set priority of an independent interrupt request of IRQ4.
11 to 8 IP5
H'0
R/W Set priority of an independent interrupt request of IRQ5.
7 to 4 IP6
H'0
R/W Set priority of an independent interrupt request of IRQ6.
3 to 0 IP7
H'0
R/W Set priority of an independent interrupt request of IRQ7.
Interrupt priorities should be determined by setting a value from H'F to H'1 to each 4-bit field. If
the value is larger, the priority is higher. When the value of H'0 is set to a field, a corresponding
interrupt is masked (initial value).
9.3.4 Interrupt Source Register (INTREQ)
INTREQ is a 32-bit readable and writable with conditions register that indicates which IRQ [n] (n
= 0 to 7) interrupt is requested to the INTC.
Even if interrupts are masked by INTPRI and INTMSK0, the INTREQ bits are not affected.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 − − − − − − −
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−−−−−−−−− −−−−−−−
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Rev. 1.00 Oct. 01, 2007 Page 250 of 1956
REJ09B0256-0100