SH7763 Datasheet, PDF (701/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 Clock Pulse Generator (CPG)
The functions of the blocks in the CPG are as follows.
(1) PLL Circuit 1
PLL circuit 1 multiples the frequency of the crystal oscillator or the clock input from the EXTAL
pin by the ratio of ×16. The multiplication ratio is selected by the combination of mode control
pins MD0, MD1, and MD2.
(2) PLL Circuit 2
PLL circuit 2 aligns the phases of the bus clock (Bck) and the clock signal output from the
CLKOUT pin that is used by the external peripheral interface.
(3) Crystal Oscillator
The crystal oscillator is a clock pulse generator used when a crystal resonator is connected to the
XTAL or EXTAL pin. The crystal oscillator can be enabled by the MD8 pin setting.
(4) Divider 1
Divider 1 generates the CPU clock (Ick), SHwy clock (SHck), peripheral module clocks (Pck0,
Pck1), and bus clock (Bck). The division ratio is selected by the combination of mode control pins
MD0, MD1, and MD2.
(5) Frequency Control Register (FRQCR)
The frequency control register is a read-only register that depends on the combination of mode
control pins MD0, MD1, and MD2.
(6) PLL Circuit 3
PLL circuit 3 multiples the frequency of the SHwy clock (SHck) by the ratio of ×4.
(7) Divider 2
Divider 2 generates the DDR-memory clocks (DDRck0, DDRck90, DDRck180, and DDRck270).
(8) PLL Control Register (PLLCR)
The PLL control register has control bits assigned for enabling or disabling the CLKOUT pin
output.
Rev. 1.00 Oct. 01, 2007 Page 635 of 1956
REJ09B0256-0100