SH7763 Datasheet, PDF (119/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 2 Programming Model
A A+1 A+2 A+3
31
23
15
7
0
7
07
07
07
0
Address A _{Byte 0 Byte 1 Byte 2 Byte 3}
15
0 15
0
Address A + 4
Word 0
Word 1
31
0
Address A + 8
Longword
A + 11 A + 10 A + 9 A + 8
31
23
15
7
0
7
07
07
07
0
Byte 3 Byte 2 Byte 1 Byte 0 ^{Address A + 8}
15
0 15
0
Word 1
Word 0 Address A + 4
31
Longword
0
Address A
Big endian
Little endian
Figure 2.7 Data Formats in Memory
For the 64-bit data format, see figure 2.5.
2.6 Processing States
This LSI has major three processing states: the reset state, instruction execution state, and power-
down state.
(1) Reset State
In this state the CPU is reset. The reset state is divided into the power-on reset state and the
manual reset.
In the power-on reset state, the internal state of the CPU and the on-chip peripheral module
registers are initialized. In the manual reset state, the internal state of the CPU and some registers
of on-chip peripheral modules are initialized. For details, see register descriptions for each section.
(2) Instruction Execution State
In this state, the CPU executes program instructions in sequence. The Instruction execution state
has the normal program execution state and the exception handling state.
(3) Power-Down State
In a power-down state, CPU halts operation and power consumption is reduced. The power-down
state is entered by executing a SLEEP instruction. There are two modes in the power-down state:
sleep mode and standby mode.
Rev. 1.00 Oct. 01, 2007 Page 53 of 1956
REJ09B0256-0100