SH7763 Datasheet, PDF (1400/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
• Write 1 to the CMDOFF bit when a CRC error (CRCERI) or command timeout error (CTERI)
occurs in the command response reception.
• Clear the FIFO by writing 1 to the CMDOFF bit when a CRC error (CRCERI) or data timeout
error (DTERI) occurs in the read data reception.
Note:
In multiblock transfer, when the command sequence is ended (write 1 to the CMDOFF
bit) before command response reception (CRPI), the command response may not be
received correctly. Therefore, to receive the command response, the command sequence
must be continued (set the RD_CONTI bit to 1) until the command response reception
ends.
Input/output pins
CLK
CMD
DAT
CMDSTRT
(START)
OPCR
(RD_CONTI)
(CMDOFF)
INTSTR0
(CMDI)
CMD17 (READ_SINGLE_BLOCK)
Command
Command response
Command
transmission
started
Read data
(CRPI)
(DTI)
(FFI)
CSTR
(CWRE)
(BUSY)
Single block read command execution sequence
(FIFO_FULL)
(REQ)
Figure 31.7 Example of Command Sequence for Commands with Read Data
(Block Size ≤ FIFO Size)
Rev. 1.00 Oct. 01, 2007 Page 1334 of 1956
REJ09B0256-0100