SH7763 Datasheet, PDF (1948/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 43 Electrical Characteristics
43.4.14 SCIF Module Signal Timing
Table 43.27 SCIF Module Signal Timing
Conditions:
V_CCQ = VDD_RTC = AV_CC = 3.0 to 3.6 V, V_CCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to
1.35 V, Ta = −20 to 75°C
Item
Input clock cycle (asynchronous)
Input clock cycle (synchronous)
Input clock pulse width
Input clock rise time
Input clock fall time
Transfer data delay time
Receive data setup time (synchronous)
Receive data hold time (synchronous)
Note: t : _Pcyc0 One Pck0 cycle time
Symbol Min.
t
8
Scyc
24
t_SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t_RXH
0.4
—
—
—
4
×
t
Pcyc0
4 × t_Pcyc0
Max.
—
—
0.6
0.8
0.8
6
×
t
Pcyc0
+
50
—
—
Unit
t
Pcyc0
t_Pcyc0
t_Pcyc0
t
Pcyc0
t
Pcyc0
ns
ns
ns
Figure
43.58
43.58
43.58
43.58
43.58
43.59
43.59
43.59
SCIFn_SCK
t_SCKW
t_Scyc
t_SCKf
t_SCKr
Figure 43.58 SCIFn_SCK Input Clock Timing
Rev. 1.00 Oct. 01, 2007 Page 1882 of 1956
REJ09B0256-0100