SH7763 Datasheet, PDF (307/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Pin Name
IRQ7/IRL7 to
IRQ4/IRL4
IRQOUT
PINT15 to PINT0
Function
I/O
External interrupt input pin Input
Interrupt request output Output
Port interrupt input pins Input
Description
Interrupt request signal input
IRL [7:4] 4-bit level-encoded
interrupt input when ICR0.IRLM1 = 0
IRQ7 to IRQ4 individual interrupt
input when ICR0.IRLM1 = 1
Notifies that an interrupt request has
generated
This pin is asserted even if the CPU
does not accept the interrupt
request, but not asserted when the
interrupt is masked.
Port interrupt request signal input
9.3 Register Descriptions
Table 9.3 shows the INTC register configuration. These registers maintain software interfaces
with the CPU (SH-4A) and are initialized by a power-on reset and a manual reset.
Table 9.3 shows the INTC register configuration. Table 9.4 shows the register states in each
operating mode.
Table 9.3 INTC Register Configuration
Name
Area 7
Abbreviation R/W P4 Address Address
Interrupt control register 0
ICR0
R/W H'FFD0 0000 H'1FD0 0000
Interrupt control register 1
ICR1
R/W H'FFD0 001C H'1FD0 001C
Interrupt priority register
INTPRI
R/W H'FFD0 0010 H'1FD0 0010
Interrupt source register
INTREQ
R/(W) H'FFD0 0024 H'1FD0 0024
Interrupt mask register 0
INTMSK0
R/W H'FFD0 0044 H'1FD0 0044
Interrupt mask register 1
INTMSK1
R/W H'FFD0 0048 H'1FD0 0048
Interrupt mask register 2
INTMSK2
R/W H'FFD4 0080 H'1FD4 0080
Interrupt mask clear register 0 INTMSKCLR0 R/W H'FFD0 0064 H'1FD0 0064
Interrupt mask clear register 1 INTMSKCLR1 R/W H'FFD0 0068 H'1FD0 0068
Interrupt mask clear register 2 INTMSKCLR2 R/W H'FFD4 0084 H'1FD4 0084
Access
Size
32
32
32
32
32
32
32
32
32
32
Rev. 1.00 Oct. 01, 2007 Page 241 of 1956
REJ09B0256-0100