SH7763 Datasheet, PDF (742/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Power-Down Mode
Initial
Bit
Bit Name Value R/W Description
16
SCIF1
0
R/W SCIF1 Module Stop Bit
When set to 1, the clock supply to the SCIF1 module is
halted.
0: SCIF1 operates
1: Clock supply to SCIF1 is halted
15
SCIF0
0
R/W SCIF0 Module Stop Bit
When set to 1, the clock supply to the SCIF0 module is
halted.
0: SCIF0 operates
1: Clock supply to SCIF0 is halted
14
SIM
0
R/W SIM Module Stop Bit
When set to 1, the clock supply to the SIM module is
halted.
0: SIM operates
1: Clock supply to SIM is halted
13
ADC
0
R/W ADC Module Stop Bit
When set to 1, the clock supply to the ADC module is
halted.
0: ADC operates
1: Clock supply to ADC is halted
12
DAC
0
R/W DAC Module Stop Bit
When set to 1, the clock supply to the DAC module is
halted.
0: DAC operates
1: Clock supply to DAC is halted
11
CMT
0
R/W CMT Module Stop Bit
When set to 1, the clock supply to the CMT module is
halted.
0: CMT operates
1: Clock supply to CMT is halted
Rev. 1.00 Oct. 01, 2007 Page 676 of 1956
REJ09B0256-0100