SH7763 Datasheet, PDF (47/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 23.38 Data Subject to Checksum Calculation ................................................................. 993
Section 25 Stream Interface (STIF)
Figure 25.1 Block Diagram of STIF ........................................................................................... 998
Figure 25.2 Transmit/Receive Data Structure in External Memory
(with 16-Byte Work Area) .................................................................................... 1015
Figure 25.3 Clock Valid Reception Timing.............................................................................. 1017
Figure 25.4 Strobe Reception Timing....................................................................................... 1019
Figure 25.5 Clock Valid Transmission Timing ........................................................................ 1021
Figure 25.6 Strobe Transmission Timing ................................................................................. 1023
Section 26 I²C Bus Interface (IIC)
Figure 26.1 Block Diagram for I²C Bus Interface .................................................................... 1025
Figure 26.2 I²C Bus Timing...................................................................................................... 1046
Figure 26.3 Master Data Transmit Format ............................................................................... 1047
Figure 26.4 Master Data Receive Format ................................................................................. 1047
Figure 26.5 Combination Transfer Format of Master Transfer ................................................ 1048
Figure 26.6 10-Bit Address Data Transmit Format .................................................................. 1048
Figure 26.7 10-Bit Address Data Receive Format.................................................................... 1049
Figure 26.8 10-Bit Address Transmit/Receive Combined Format ........................................... 1049
Figure 26.9 Data Transmit Mode Operation Timing ................................................................ 1051
Figure 26.10 Data Receive Mode Operation Timing................................................................ 1053
Section 27 Serial Communication Interface with FIFO (SCIF)
Figure 27.1 Block Diagram of SCIF......................................................................................... 1061
Figure 27.2 SCIFn_RTS Pin (n = 0, 1) ..................................................................................... 1062
Figure 27.3 SCIFn_CTS Pin (n = 0, 1) ..................................................................................... 1063
Figure 27.4 SCIFn_SCK Pin (n = 0, 1)..................................................................................... 1064
Figure 27.5 SCIFn_TXD Pin (n = 0, 1) .................................................................................... 1064
Figure 27.6 SCIFn_RXD Pin (n = 0, 1).................................................................................... 1065
Figure 27.7 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, and Two Stop Bits) ......................................... 1094
Figure 27.8 Sample SCIF Initialization Flowchart ................................................................... 1097
Figure 27.9 Sample Serial Transmission Flowchart ................................................................. 1098
Figure 27.10 Sample SCIF Transmission Operation
(Example with 8-Bit Data, Parity, One Stop Bit)................................................ 1100
Figure 27.11 Sample Operation Using Modem Control (SCIF_CTS)...................................... 1100
Figure 27.12 Sample Serial Reception Flowchart (1)............................................................... 1101
Figure 27.12 Sample Serial Reception Flowchart (2)............................................................... 1102
Figure 27.13 Sample SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)................................................ 1103
Rev. 1.00 Oct. 01, 2007 Page xlvii of lxvi