SH7763 Datasheet, PDF (727/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
(2) PRESET input during normal operation
It is necessary to ensure the PLL oscillation settling time when the PRESET input during normal
operation.
EXTAL
input
CLKOUT
output
PRESET
input
STATUS[1:0]
output
LL (normal)
HH (reset)
LL (normal)
PLL oscillation
settling time
Reset holding
time
Figure 17.4 STATUS Output by Reset input during Normal Operation
(3) PRESET input during Sleep Mode
It is necessary to ensure the PLL oscillation time when power-on reset generates by the PRESET
pin low revel input during sleep mode.
EXTAL
input
CLKOUT
output
PRESET
input
STATUS[1:0]
output
HL (sleep)
HH (reset)
LL (normal)
PLL oscillation
settling time
Reset holding
time
Figure 17.5 STATUS Output by Reset input during Sleep Mode
Rev. 1.00 Oct. 01, 2007 Page 661 of 1956
REJ09B0256-0100