SH7763 Datasheet, PDF (1057/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
(1) Write to PHY interface
register
ET_MMD = 0
ET_MDC = 1
(2) Read from PHY
interface register
ET_MMD = 0
ET_MDC = 1
ET_MDI is read data
ET_MDC
ET_MDI
(1) (2) (3)
1-bit data read timing
relatinship
(2) Write to PHY interface
register
ET_MMD = 0
ET_MDC = 0
Figure 23.35 1-Bit Data Read Flowchart
(1) Write to PHY interface
register
ET_MMD = 0
ET_MDC = 0
ET_MDC
ET_MDO
(1)
Independent bus release
timing relationship
Figure 23.36 Independent Bus Release Flowchart (IDLE in Write in Figure 23.33)
23.5.5 Mll-RMII Interface Conversion
This LSI supports an RMII interface. The RMII signals are generated by converting the MII
signals in the MII-RMII conversion circuit.
(1) Clock
REF50CK (50 MHz) from the RMII interface is divided and ET_TX-CLK/ET_RX-CLK (25 MHz
or 2.5 MHz) is output.
Rev. 1.00 Oct. 01, 2007 Page 991 of 1956
REJ09B0256-0100