SH7763 Datasheet, PDF (1478/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
33.5.5 Initialization Sequence
Figure 33.3 shows an example of the initialization sequence.
Start
HAC cold reset (HACCR = H'0000 0A00)
HAC
module
initialiation
Start DMA transfer (Receiver/Transmitter)
(HACCR = H'0000 0020)
TX, RX enable
(set HACACR = H'03E0 0000: 20-bit DMATX,
slot 1 and slot 2 are atomic control)
Codec ready?
No
(HACCR = H'0000 8000)
Yes
Set DMAC
Set read address H'26 (Power-down Ctrl/Stat)
(HACCSAR = H'000A 6000)
External
codec
device
initialiation
External codec internal status
No
ADC, DAC, Analog, REF = ready?
()HACCSDR = H'0000 00F0
Yes
Set read volume and sampling rate
(1) HACACR = H'0000 0000
(2) Set HACCSAR and HACCSDR
(3) HACACR = H'01E0 0000
Note: Refer to section 14, Direct Memory Access Controller (DMAC).
Figure 33.3 Initialization Sequence
Rev. 1.00 Oct. 01, 2007 Page 1412 of 1956
REJ09B0256-0100