SH7763 Datasheet, PDF (1085/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
(3) Strobe Reception
(a) Strobe Reception Interface
• Timing chart
Figure 25.4 shows the timing of the strobe reception interface.
ST_STRB (input)
ST_START (input)
don't care
ST_VALID (input)
ST_REQ (output)
don't care
ST_D7 to ST_D0
(input)
Up to 8 bytes can be received
Figure 25.4 Strobe Reception Timing
• Active level setting for ST_STRB, ST_START, ST_VALID, and ST_REQ pins
The active levels of the ST_STRB, ST_START, ST_VALID, and ST_REQ pins can be set by
the STRB, STAT, VLD, and REQ bits in STIMDR, respectively.
• Selection of ST_REQ pin usage
Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR.
When usage of the ST_REQ pin is enabled, the ST_REQ pin is asserted when the free space in
the transmit/receive FIFO for stream data becomes eight bytes or less. After assertion, up to
eight bytes of data can be received. The ST_REQ pin is negated when the free space in the
FIFO has become 192 bytes or more.
When usage of the ST_REQ pin is disabled, the ST_REQ pin output is fixed at low or high
depending on the REQ bit value.
(b) Receive Packet Length
The receive packet length can be selected from 188 and 192 bytes.
(c) Work Area
The size of the work area in external memory can be selected from among 0, 16, 32, and 48 bytes.
Rev. 1.00 Oct. 01, 2007 Page 1019 of 1956
REJ09B0256-0100