SH7763 Datasheet, PDF (1610/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.35 Time Stamp Register (TSRH/TSRL)
TSR is a register to store the current time stamp value. The time stamp is updated when the SOF
bit in IFR0 is set to 1. The value of the time stamp when the SOF mark function is enabled and the
SOF packet is broken remains as previous one.
TSR is handled as an 11-bit (TSR[10:0]) register in the USBF which consists of TSR[10:8] bits in
TSRH and TSR[7:0] bits in TSRL. Although TSRH can be read directly, TSRL is read via an 8-bit
temporary register. Therefore, the registers should be accessed in the order of TSRH and TSRL in
byte units. TSRL cannot be read singly.
• TSRH
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—————————————
TSR[10:8]
Initial value: — — — — — — — — 0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 8 
7 to 3 
2 to 0 TSR[10:8]
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
All 0
R Reserved
These bits are always read as 0.
All 0
R Upper Three Bits of Time Stamp Data
Rev. 1.00 Oct. 01, 2007 Page 1544 of 1956
REJ09B0256-0100