SH7763 Datasheet, PDF (105/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 2 Programming Model
(3) Control Registers
Control registers comprise the global base register (GBR) and status register (SR), which can be
accessed in both processing modes, and the saved status register (SSR), saved program counter
(SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register
(DBR), which can only be accessed in privileged mode. Some bits of the status register (such as
the RB bit) can only be accessed in privileged mode.
(4) System Registers
System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure
register (PR), and the program counter (PC). Access to these registers does not depend on the
processing mode.
(5) Floating-Point Registers and System Registers Related to FPU
There are thirty-two floating-point registers, FR0–FR15 and XF0–XF15. FR0–FR15 and XF0–
XF15 can be assigned to either of two banks (FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1–
FPR15_BANK1).
FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating-
point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0–
XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix
XMTRX.
System registers related to the FPU comprise the floating-point communication register (FPUL)
and the floating-point status/control register (FPSCR). These registers are used for communication
between the FPU and the CPU, and the exception handling setting.
Register values after a reset are shown in table 2.1.
Rev. 1.00 Oct. 01, 2007 Page 39 of 1956
REJ09B0256-0100